1. Field of the Invention
The present invention relates generally to a high speed embedded DRAM with a SRAM-like interface, and more particularly pertains to a high speed embedded DRAM with a single port SRAM-like interface which is used in short-cycle high-speed data operations.
2. Discussion of the Prior Art
To further improve the speed of DRAM memory, several embedded DRAMs with a SRAM-like interface have been proposed recently. A 1T(Transistor)-SRAM is described in several issued U.S. patents, and is a popular approach. In the disclosed 1T-SRAM, a dual port SRAM is used as a cache between a DRAM and the outside world. In general, the size of the dual port SRAM is about 2.5× larger than that of a single port SRAM, and is about 15× larger than the same capacity DRAM. In some embedded applications, not only the speed, but also the size of the memory is critical. This is especially true for some applications, for example, a router switch, network processor, etc. where a large memory size is required. In the disclosed 1T-SRAM, the efficiency of pipeline data flow is low, and the prior art does not discuss sharing of internal buses to save chip area. Data congestion also appears to be a substantial problem with the design.